Logic Synthesis Using Synopsys Design Compiler
Logic synthesis is the process by which an abstract form of desired circuit behavior, such as RTL, is transformed into a design implementation in terms of logic gates. This transformation is carried out using CAD tools. This section discusses logic synthesis using Synopsys Design Compiler tool. The basic flow of using any logic synthesis tool would be:
- Part I
- Setup search path and design library
- Setup technology libraries
- Read RTL files
- Link design
- Check design quality
- Define design environment
- Part II
- Define system interface
- Setup design constraints and goals
- Part III
- Compile the design
- Analyze results and generate reports
- Write out the netlist and associated files
Perl
- Introduction
- Scalars
- Arrays
- Hashes
- Subroutines
- Library
- Packages
- Modules
- Regular Expressions
