The basic flow of using any logic synthesis tool would be:
- Part I
- Setup search path and design library
- Setup technology libraries
- Read RTL files
- Link design
- Check design quality
- Define design environment
- Part II
- Define system interface
- Setup design constraints and goals
- Part III
- Compile the design
- Analyze results and generate reports
- Write out the netlist and associated files
Part III
Compile the design
Once the design has been read and appropriate constraints applied, the next step is to compile the design to obtained a technology mapped optimized netlist.
The optimization process consists of three steps:
- Architectural - The architectural optimization, sometimes called high level synthesis, works on the HDL code. Optimization is based on the HDL coding style and constraints set. This phase includes tasks such as sharing common sub-expressions, sharing resources, and selecting DesignWare components. These tasks, with the exception DesignWare selection, occur on an unmapped design. After this optimization, the design is represented as GTECH library parts.
- Logic Level - The logic level optimization is broken into two processes: structuring and flattening. Both of these processes work on GTECH design.
- Structuring: Optimization during this phase is influenced by the constraints set. This process adds intermediate variables and logic structure to the design that can help reduce area. The tool searches for sub functions that can be factored out and evaluates these factors based on size of the factor an number of times it appears in the design. The tool turns the sub functions that reduce the logic most into intermediate variables and factors them out of the design equations.
- Flattening: The tool converts combinational logic paths into a sum of products representation. The conversion is independent of constraints. During this process, the tool removes all intermediate variables from the design. This process increases CPU time and can increase area.
