Logic Synthesis Using Synopsys Design Compiler

The basic flow of using any logic synthesis tool would be:
  • Part I
    • Setup search path and design library 
    • Setup technology libraries 
    • Read RTL files 
    • Link design
    • Check design quality 
    • Define design environment
  • Part II
    • Define system interface 
    • Setup design constraints and goals
  • Part III
    • Compile the design 
    • Analyze results and generate reports
    • Write out the netlist and associated files

Part 0 - Optional

Ad-Hoc Design Compiler Notes:  

There are different type of design objects categorized by design compiler. These are:
  • Design : It corresponds to the circuit description that performs some logical function, and can be standalone or may include sub designs. Sub designs are also treated as another designs by the tool. 
  • Cell : It is the instantiated name of the sub-design in the design, sometimes referred to as instance. 
  • Reference: This is the definition of the original design to which cell or instance refers to. 
  • Port: These are the primary inputs, outputs or IO's of the design
  • Pin : It corresponds to the inputs, outputs of IO's of cells in the design. 
  • Net : These are signal names.
  • Clock : The port or pin identified as a clock source. 
  • Library : Collection of technology specific cells that the design is targeting for synthesis; or linking for reference.
Various list_* command exists to query the contents of tool memory:
  • list_libs 
    • List all the libraries loaded into the memory
  • list_designs
    • List all the designs loaded into the memory
  • list_files 
    • List paths to all the paths loaded into the memory
  • list_instances 
    • List instance details for each designs loaded into the memory
The design objects can be queried using:
  • get_designs
    • Retrieves all the designs
  • get_ports
    • Retrieves all the ports
  • get_cells
    • Retrieves all the instances of the design
  • get_references
    • Retrieves all the instances of the design
  • get_pins
    • Retrieves all the pins of the design
  • get_nets 
    • Retrieves all the nets of the design
  • get_libs
    • Retrieves all the libraries of the design which matches search pattern
  • get_lib_cells
    • Retrieves all the library cell which matches search pattern
  • get_lib_pins
    • Retrieves all the library cell pins which matches search pattern
  • get_clocks
    • Retrieves all the clocks of the design
  • get_generated_clocks
    • Retrieves all the generated clocks of the design
  • all_designs
    • Retrieves all the designs loaded
  • all_inputs
    • Retrieves all the input ports of the design 
  • all_outputs
    • Retrieves all the output ports of the design
  • all_registers
    • Retrieves all the registers of the design
  • all_clocks
    • Retrieves all the clock of the design
set_attribute and get_attribute can be used to set and retrieve attribute on design objects. The attributes can be removed from the tool using remove_attribute command. 

report_design would provide summary of the entire design. report_attribute would provide report of all attributes currently been set on the design. 
  • report_attribute {ex28nm_ss1p08v125c/BUFFX8} 
  • report_attribute {ex28nm_ss1p08v125c/BUFFX8/Z} 
The design compiler environment can be reset/cleared using remove_design command. To remove designs:

  • remove_design -designs 
    • Removes all designs
    • remove_design -hierarchy 
      • Removes all designs in hierarchy
      • remove_design -all 
        • Removes all designs and libraries
        The SVF file generated by the design compiler can be turned off or can have custom defined name using set_svf command. Note that, this should be done before define_design_lib command to avoid creation of "default.svf". 
        • set_svf -off
          • Turns off SVF file creation
        • set_svf my_design.svf
          • Creates my_design.svf file for design optimization guidance

        Sample Design Compiler Script:
        set_svf -off
        define_design_lib -path ./TOP_WORK TOP_WORK

        set search_path {. \
        ../rtl \
        ../scripts \
        ../libs \
        ../models \
        ../ips \
        }

        set target_library     {ex28nm_ss1p08v125c.db}
        set link_library       {* ex28nm_ss1p08v125c.db} 
        set synthetic_libarary {}
        set symbol_library     {} 

        analyze -work ChipLevel_WORK -format verilog { \
        Block1.v \
        Block2.v \
        TOP.v \
        }

        elaborate -work TOP_WORK TOP
        link
        check_design
        exit

        Part I

        Setup search path and design library

        The search path is used to list all the directories where the tool can look in for files. 
        • search_path variable holds the list of all directories. 
        • This can be set using: 
          • set search_path {. ../lib ../rtl ../scripts ../models} 
        The design library is used to store intermediate files to be used by the tool. 
        • define_design_lib variable holds the logical design library name and its path.  
        • This can be set using:
          • define_design_lib -path ./work WORK
        • This creates a directory work in the current directory and maps it with a logical name of WORK to be used within the tool. 
        • The list of loaded design libraries can be viewed using report_design_lib command. 
          • report_design_lib -libraries 


        Setup technology libraries 

        The tool needs to know what libraries to use when synthesizing your RTL to gates. There are different type of libraries with different definition. 
        • Target Library: These libraries define the semiconductor vendor's set of standard cells and its associated information, such as cell names, cell pin names, delay arcs, pin loading, design rules and operation condition. The cells from these libraries are used to actually map the inferred RTL logic into gates. 
          • target_library variable holds the list of all the target libraries. 
          • This can be set using:
            • set target_library {ex28nm_ss1p08v125c.db}
          • All the cells from ex28nm_ss1p08v125c.db will be used to mapped inferred RTL logic into gates. 
        • Link Library: These libraries define the semiconductor vendor's set of standard cells and its associated information, such as cell names, cell pin names, delay arcs, pin loading, design rules and operation condition. The cells from these libraries are not used for mapping purpose, but for cell resolution of reused designs, macros, etc. 
          • link_library variable holds the list of all the link libraries to be used to resolve design references. 
          • This can be set using:
            • set link_library {* ex28nm_ss1p08v125c.db}
          • All the cells from current memory and ex28nm_ss1p08v125c.db will be used to resolve any cell reference. Note * in the first link library value, which indicates to use the designs in the memory to resolve cell references first, before looking into next link library. 
        • Synthetic Library: Design compiler implements standard synthetic library which implements standard HDL operators and it automatically uses it. If we were to use additional DesignWare libraries, these can be specified using synthetic_library variable to be used for optimization purposes. 
          • This can be set using:
            • set synthetic_library {dw_ip01.sldb}
        • Symbol Library: This is used to create netlist view using cell symbols which are part of symbol libraries. 
          • symbol_library variable holds the list of all the symbol libraries to be used to create GUI view of schematic. 
          • This can be set using:
            • set symbol_library {* ex28nm_ss1p08v125c.sdb}
        Note: Extensions .db are for target and link libraries, .sldb are for synthetic libraries and .sdb for symbol libraries. The target and link libraries can also be present in .lib format and symbol libraries in .slib format. 


        Read RTL files

        There are two methods to read files into Design Compiler:
        • Multi step read method
        • Single step read method
        Multi step read method: This comprises of analyze command followed by elaborate command. 
        • analyze: This command performs the following:
          • Reads an HDL source file and performs HDL syntax checking and Synopsys rule checking. 
          • Checks files for errors while building generic logic for the design. 
          • Creates HDL library object in an intermediate format. 
          • Stores the intermediate files in a location specified in define_design_lib variable.
          • Intermediate files:
            • VHDL Intermediate files: 
              • The intermediate files include .syn, .st and .mr files. 
              • *.syn files are binary files which will be used by elaborate command
              • *.st files store intermediate results. 
              • *.mr files stores most recent analyzed architecture for an entity. It holds the name of the architecture used with an entity declaration. 
            • Presto-Verilog Intermediate files (When Presto is ON, by default): 
              • The intermediate files include .pvl and .mr files. 
              • *.pvl files store intermediate results. 
              • *.mr files store module references. 
            • Verilog Intermediate files (When Presto is OFF): 
              • The intermediate files include %verilog.syn, .mr and %verilog_verilog.syn files. 
              • %verilog.syn files are binary files used by elaborate command. 
              • *.mr files store module references. 
              • %verilog_verilog.syn are binary files used by elaborate command. 
        • elaborate: The analyze command performs the following:
          • Translates the design into its GTECH representation. 
          • Allows changing of parameter values defined in the source code. 
            • elaborate TOP -param width=>32,ports=>8
          • Allow VHDL architecture selection. 
          • Replaces the HDL arithmetic operators in the code with DesignWare components. 
          • Performs link automatically. 
        Single step read method: This used read_file command which performs both the analyze and elaborate functions in one step. 
        • read_file: This command performs the following: 
          • Performs the same operation as analyze and elaborate in one step. 
          • It doesn't create any intermediate files for Verilog, but creates .mr and .st files for VHDL. 
          • It doesn't execute the link command automatically. 
          • Allows several format of files to be read. The following format is supported: 
            • ddc - Synopsys internal database format (default)
            • db - Synopsys internal database format (libraries only) 
            • verilog - IEEE Standard Verilog
            • sverilog - IEEE Standard SystemVerilog
            • vhdl - IEEE Standard VHDL
            • equation - Synopsys equation format 
            • pla - Berkeley (Espresso) PLA format
            • st - Synopsys State Table format


        Link design

        The link command locates all the design and library components and connects them to the current design. Once this is done design is complete. 


        Check design quality 

        The check_design command reports any warnings encountered during static design rule checks (LINT). 

        Define design environment 

        The design environment refers to the operating conditions under which the design is expected to operate reliably. It also have to provide information about probable interconnect characteristics and system interface electrical requirements. These design environmental conditions are derived from various technology libraries loaded earlier in design setup stage.
        • list_libs command is used to see all the libraries loaded in the memory
        • report_lib command is used to set the details of any specific library
        Operating Conditions: The operating conditions consist of process, voltage and temperature specifications. The effects each of these can have on the design need to be considered during synthesis and timing analysis. During timing analysis, tool must consider the worst-case and best-case scenarios for the expected variations in the temperature, voltage and process factors. 
        •  The operating conditions available within technology library can be viewed using: 
          • report_lib -operating_condition ex28nm_ss1p08v125c.db
          • report_operating_condition -library ex28nm_ss1p08v125c.db
        • The design operating condition can be set using:
          • set_operating_condition -library ex28nm_ss1p08v125c.db WCCOM
        • To see what environmental conditions are currently set on the design can be viewed using:
          • report_design 

        Interconnect Characteristics: During RTL design stage, there is no information about the placement and routing characteristics. This places an requirement to accurately model and estimate the effect of wire length and fanout on the resistance, capacitance and area of the net. 


        Wire Load Model: A typical library description of wire load model would be as shown below: 

        Name           :   100x100
        Location       :   ex28nm_ss0p95v125c
        Resistance     :   0.002173
        Capacitance    :   0.029296
        Area           :   0.01
        Slope          :   30.2854
        Fanout   Length   Points Average Cap Std Deviation
        ---------------------------------------------------
             1     8.28
             2    18.49
             ...
             7    80.36
             8    95.27

         The resistance, capacitance and area mentioned are per unit length values. The slope is used to linear extrapolate for fanout values not mentioned in the table above. 

         For illustration, let us compute the length for fanout value of 10. This would be computed as: 
        Length(fanout == 10) = Length(fanout ==8) + (10-8)* Slope = 95.27 + (2 * 30.2854) = 155.8408 

        Then, 
        Resistance  = 0.002173 * 155.8408 
        Capacitance = 0.029296 * 155.8408 
        Area        = 0.01 * 155.8408 

         The units of resistance, capacitance and area are provided in the technology library. 

         The wire load model can be specified using: 
        • set_wire_load_model -library ex28nm_ss0p95v125c -name 100x100

        Wire Topology: Once the resistance and capacitance estimates of the pre-layout interconnect are determined, the next important thing is to estimate the structure of the interconnect. The interconnect delay depends upon the interconnect resistance and capacitance along the path.Thus, this delay can be different depending on the topology assumed for the net. 

         The different topology of net are: 
        • Best-case tree: It is assumed that the destination (load) pin is physically adjacent to the driver. Thus, none of the wire resistance is in the path to the destination pin. All the wire capacitance and pin capacitance from other fanout pins still acts as a load on the driver pin. 
        • Balanced tree: It is assumed that each destination pin is on a separate portion of the interconnect wire. Each path to the destination sees an equal portion of total wire resistance and capacitance. 
        • Worst-case tree: It is assumed that all destination pin are together at far end of the wire. Thus, each destination pin sees the total wire resistance and total wire capacitance.
        The wire topology can be viewed by querying operating condition listed as "Interconnect Model". This can be done using: 
        • report_lib -operating_condition ex28nm_ss1p08v125c.db
        • report_operating_condition -library ex28nm_ss1p08v125c.db
        Hierarchical Wire Load Model: 
        When a net crosses a hierarchical boundary, different wire load models can be applied to different parts of net in each hierarchical boundary based on wire load mode. Three wire load mode exists:
        • top: All nets within the hierarchy inherit the wire load model of the top level, that is, any wire load models specified at lower level blocks are ignored. Thus, the top level wire load model takes precedence. 
        • enclosed: The wire load model of a block that fully encompasses the net is used for the entire net.  
        • segmented: Each segment of a net gets it wire load model from the block that encompasses the net segment. 
        The wire load mode can be set using:
        • set_wire_load_mode enclosed
        Area based Wire Load Model: Typically, a wire load model is selected based upon chip area of the block. These are defined in technology library as area based wire load selection group. Typically, there would be many such selection groups. One of them can be set using: 
        • set_wire_load_selection_group <area_based_wlm_group>
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